1. Field of the Invention
Embodiments of the present invention generally relate to an apparatus and method that is used to manufacture a semiconductor device. More particularly, the invention is directed to an apparatus and method that is used to thermally process a substrate.
2. Background of the Related Art
The integrated circuit (IC) market is continually demanding greater memory capacity, faster switching speeds, and smaller feature sizes. One of the major steps the industry has taken to address these demands is to change from batch processing silicon wafers in large furnaces to single wafer processing in a small chamber.
During such single wafer processing the wafer is typically heated to high temperatures so that various chemical and physical reactions can take place in multiple IC devices defined in the wafer. Of particular interest, favorable electrical performance of the IC devices requires implanted regions to be annealed. Annealing recreates a more crystalline structure from regions of the wafer that were previously made amorphous, and activates dopants by incorporating their atoms into the crystalline lattice of the substrate, or wafer. Thermal processes, such as annealing, require providing a relatively large amount of thermal energy to the wafer in a short amount of time, and thereafter rapidly cooling the wafer to terminate the thermal process. Examples of thermal processes currently in use include Rapid Thermal Processing (RTP) and impulse (spike) annealing. While such processes are widely used, current technology is not ideal. It tends to ramp the temperature of the wafer too slowly and expose the wafer to elevated temperatures for too long. These problems become more severe with increasing wafer sizes, increasing switching speeds, and/or decreasing feature sizes.
In general, these thermal processes heat the substrates under controlled conditions according to a predetermined thermal recipe. These thermal recipes fundamentally consist of a temperature that the semiconductor substrate must be heated to the rate of change of temperature, i.e., the temperature ramp-up and ramp-down rates and the time that the thermal processing system remains at a particular temperature. For example, thermal recipes may require the substrate to be heated from room temperature to distinct temperatures of 1200° C. or more, for processing times at each distinct temperature ranging up to 60 seconds, or more.
Moreover, to meet certain objectives, such as minimal inter-diffusion of materials between different regions of a semiconductor substrate, the amount of time that each semiconductor substrate is subjected to high temperatures must be restricted. To accomplish this, the temperature ramp rates, both up and down, are preferably high. In other words, it is desirable to be able to adjust the temperature of the substrate from a low to a high temperature, or visa versa, in as short a time as possible.
The requirement for high temperature ramp rates led to the development of Rapid Thermal Processing (RTP), where typical temperature ramp-up rates range from 200 to 400° C./s, as compared to 5-15° C./minute for conventional furnaces. Typical ramp-down rates are in the range of 80-150° C./s. A drawback of RTP is that it heats the entire wafer even though the IC devices reside only in the top few microns of the silicon wafer. This limits how fast one can heat up and cool down the wafer. Moreover, once the entire wafer is at an elevated temperature, heat can only dissipate into the surrounding space or structures. As a result, today's state of the art RTP systems struggle to achieve a 400° C./s ramp-up rate and a 150° C./s ramp-down rate.
To resolve some of the problems raised in conventional RTP type processes various scanning laser anneal techniques have been used to anneal the surface(s) of the substrate. In general, these techniques deliver a constant energy flux to a small region on the surface of the substrate while the substrate is translated, or scanned, relative to the energy delivered to the small region. The scanned laser anneal, RTP and other thermal processes, which may include pulsed laser anneal techniques, are commonly performed to thermal process the devices formed on the surface of the substrate.
To help reduce the processing time and improve the performance of a thermal process performed in a thermal processing chamber it is common to preheat the substrate to a moderate temperature to improve throughput, reduce the induced thermal stress, and improve the process results by reducing the temperature range that the substrate needs go through during the thermal process. Typically, the preheat temperature used in RTP and laser annealing processes range from about 450° C. to about 700° C. In most cases, the preheat processes are performed by positioning a substrate on a heated substrate support, which is heated by embedded resistive heating elements positioned in the substrate support, or is heated by lamps. One problem that arises in the heated substrate support configuration is that when not all regions of the substrate come into good thermal contact with the heated substrate support at the same time, the substrate will deform due to the varying thermal expansion of the substrate created by the varying temperatures within the substrate. It has been found that in cases where the center of a substrate comes in contact with the support first, the substrate will deform into a shape (e.g., concave shape) that can greatly affect process results achieved from the center to edge of the substrate. In view of the above, there is a need for an apparatus and method of receiving a cold wafer on a heated support so that the thermal variation across the substrate during the initial exposure to a heated substrate support will not affect the process results.
Another issue that arises is that as device sizes decrease the tolerance to temperature variation across the substrate has become very low, such that the alignment and positioning of a substrate relative to the substrate support can have an affect on the uniformity of the process results achieved on the substrate. Due to thermal uniformity and/or substrate breakage concerns it is common in some thermal processing configurations to use a shadow ring to shadow and/or retain a portion of the edge of the substrate. Typically, since most semiconductor manufacturers are concerned about the process results across the substrate surface except a 3 mm (˜0.12 inches) region at the edge of the substrate, this is the only area over which the shadow ring can cover to reduce thermal effects created at the edge of the substrate. However, it is typical for most conventional automated systems for the robot to have a positioning error of about +/−0.010 inches. Thermal uniformity results are generally affected by substrate misplacements on the order of about 0.004 inches. To resolve these types of issues a highly accurate or precise robots are often required to precisely place a substrate within a desired position in the processing chamber. These types of solutions are often expensive and are not reliable due to variations in placement due to wear on the robot, or temperature variations in the robot assembly found after the transferring the first versus the 25th wafer in a process sequence. The complexity and cost of the system also generally increase as the need for high temperature robotic components (e.g., bearings), precise and expensive motors, complex control systems, and reliable rotating vacuum seals. Therefore, there is a need for a simple, inexpensive, and reliable method and apparatus for accurately positioning and aligning the substrate to the various chamber components.